asahi kasei [akd5701-a] 2006 / 06 - 1 - general description akd5701-a is an evaluation board for the portable di gital audio 16bit a/d converter, AK5701. akd5701-a also has the digital audio interf ace and can achieve the interface with digital audio systems via opt-connector. ? ordering guide akd5701-a --- evaluation board for AK5701 (cable for connecting with printer port of ibm-at compatible pc and control software are packed with this. this cont rol software does not support windows nt.) function ? dit with optical output ? rca connector for an external clock input ? 10pin header for serial control interface ak4114 (dit) 10pin header control data 10pin header dgnd opt out AK5701 vd avdd dsp 1 dvdd agnd mic 5v regulator 3.3v 10pin header dsp 2 ext/bclk rin1/ rin2 lin1/ lin2 ext/lrck clock gen figure 1. akd5701-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. AK5701 evaluation board rev.1 a kd5701- a
asahi kasei [akd5701-a] 2006 / 06 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, dvdd and vd are supplied from the regulator. [reg] (red) = 5v [avdd] (orange) = open [dvdd] (orange) = open [vd] (orange) = 2.7 3.6v : for logic [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground 1-2) when avdd, dvdd and vd are not supplied from the regulator. [reg] (red) = ?reg? jack should be open. [avdd] (orange) = 2.4 3.6v : for avdd of AK5701 (typ. 3.0v) [dvdd] (orange) = 1.6 3.6v : for dvdd of AK5701 (typ. 3.0v) [vd] (orange) = 2.7 3.6v : for logic [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the AK5701 and ak4114 should be reset once by bringing sw1, 2 ?l? upon power-up. ? evaluation mode in case of AK5701 evaluation using ak4114, same audio interface format should be set for both AK5701 and ak4114. about AK5701?s audio interface format, refer to datasheet of AK5701. about ak4114?s audio interface format, refer to table 2 in this manual. applicable evaluation mode (1) evaluation of pll, master mode (default) (2) evaluation of pll, slave mode (pll reference clock: mcki pin) (3) evaluation of pll, slave mode (p ll reference clock: bclk or lrck pin) (4) evaluation of using dit of ak4114 (opt-connector): ext, slave mode (5) slave & bypass mode (6) bypass mode
asahi kasei [akd5701-a] 2006 / 06 - 3 - (1) evaluation of pll, master mode (default) connect port2 dsp1 with dsp. figure below shows port2 pin assign. port2 gnd gnd nc nc nc vd sdto lrck bclk mcko a) set up jumper pins of mcki clock when using x?tal as mcki clock, x?tal of 11. 2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz can be set to x1. x?tal of 11.2896mhz (default) is set on the akd5701-a. when an external clock (11.2896mhz, 12mhz, 12.288m hz, 13mhz, 24mhz or 27mhz) is supplied through an rca connector (j3: ext/bclk), select extclk/bclk on jp16 (xti) and select extclk/bclk on jp19 (mclk_sel). jp14 (ext1) and r20 should be properl y selected in order to match the output impedance of the clock generator. jp16 xti jp19 mclk_sel mcki jp11 mkfs extclk /bclk 5701- mcko extclk /bclk 4114- mcko 256fs 512fs 1024fs mck o b) set up jumper pins of bclk clock output frequency (32fs/64fs) of bclk should be set by ?bcko1-0 bit? in the AK5701. there is no necessity for set up jp12. jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck
asahi kasei [akd5701-a] 2006 / 06 - 4 - (2) evaluation of pll, slave mode (pll reference clock: mcki pin) connect port4 (dsp2) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki a) set up jumper pins of mcki clock x?tal of 11.2896mhz (default) is set on the akd5701-a. in this case, the AK5701 corresponds to pll reference clock of 11.2896mhz. in this evaluation m ode, the output clock from mcko pin of the AK5701 is supplied to a divider (u3: 74vhc4040), exbclk and lrck clocks are generated by the divider. then ?mcko bit? in the AK5701 should be set to ?1?. when an external clock is supplied through an rca connector (j3: ext/bclk), select extclk/bclk on jp16 (xti) and select extclk/bclk on jp17 (mclk_ sel). jp14 (ext1) and r20 should be properly selected in order too match the output impedance of the clock generator. jp16 xti jp19 mclk_sel mcki jp11 mkfs extclk /bclk 5701- mcko extclk /bclk 4114- mcko 256fs 512fs 1024fs mck o b) set up jumper pins of bclk clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck
asahi kasei [akd5701-a] 2006 / 06 - 5 - (2-a) in the case of using ak4114. *this mode is bclk=64fs, lrck=1fs only. set up jumper pins of mcki clock *in the case of using x1, jp16 should be open. jp16 xti jp19 mclk_sel jp11 mkfs & 9 5 & 9 5 256fs 512fs 1024fs mck o set up jumper pins of bclk clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck set up jumper pins of lrck clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk
asahi kasei [akd5701-a] 2006 / 06 - 6 - (3) evaluation of pll, slave mode (pll reference clock: bclk or lrck pin) connect port4 (dsp2) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki a) set up jumper pins of mcki clock jp16 xti jp19 mclk_sel mcki extclk /bclk 5701- mcko extclk /bclk 4114- mcko b) set up jumper pins of bclk clock when an external clock is supplied through a rca connector j3 (ext/bclk), j4 (ext/lrck), jp14 (ext1) and r20, jp15 (ext2) and r21 should be properly selected in order to much the output impedance of the clock generator. jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck
asahi kasei [akd5701-a] 2006 / 06 - 7 - (4) evaluation of ext, slave mode connect port4 (dsp2) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki a) set up jumper pins of mcki clock port4 (dsp2) is used. jp19 (mcki_sel) should be open. b) set up jumper pins of bclk clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck d) set up jumper pins of data ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk
asahi kasei [akd5701-a] 2006 / 06 - 8 - (5) slave & bypass mode connect port4 (dsp2) and port2 (dsp1) with dsp. figure below shows port4 and port2 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki port2 gnd gnd nc nc nc vd sdto lrck bclk mcko a) set up jumper pins of mcki clock port4 (dsp2) is used. jp19 (mcki_sel) should be open. b) set up jumper pins of bclk clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck d) set up jumper pins of data ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk
asahi kasei [akd5701-a] 2006 / 06 - 9 - (6) bypass mode $ p o o f d u 1 0 3 5 % 4 1
b o e 1 0 3 5 % 4 1
x j u i % 4 1 figure below shows port4 and port2 pin assign. port4 gnd gnd nc nc sdto vd exsdti exlrck exbclk mcki port2 gnd gnd nc nc nc vd sdto lrck bclk mcko a) set up jumper pins of mcki clock port4 (dsp2) is used. jp19 (mcki_sel) should be open. b) set up jumper pins of bclk clock jp12 bclk 32fs 16fs 64fs ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk c) set up jumper pins of lrck clock jp13 lrck 1fs 2fs ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck d) set up jumper pins of data ext jp18 lrck_sel lrck/ dit extlrck/ dit ext lrck ext jp17 bclk_sel bclk/ dit extbclk/ dit ext bclk
asahi kasei [akd5701-a] 2006 / 06 - 10 - ? dip switch set up [sw2] (mode): mode setting of ak4114 on is ?h?, off is ?l?. no. name on (?h?) off (?l?) 1 dif0 2 dif1 ak4114 audio format setting see table 2 3 ocks0 4 ocks1 master clock frequency select see table 3 table 1. mode setting resistor for AK5701 set up for ak4114 sw3 m/s dif1 dif0 dif1 dif0 daux 0 1 0 0 0 24bit, left justified master 0 1 1 0 1 24bit, i 2 s master default 1 1 0 1 0 24bit, left justified slave 1 1 1 1 1 24bit, i 2 s slave table 2. setting for AK5701 and ak4114 audio interface format no. ocks1 ocks0 mcko1 x?tal 0 0 0 256fs 256fs default 2 1 0 512fs 512fs table 3. master clock frequency select for ak4114 (stereo mode) ? other jumper pins set up
asahi kasei [akd5701-a] 2006 / 06 - 11 - 1. jp1 (gnd) : analog ground and digital ground open : separated. short : common. (the conn ector ?dgnd? should be open.) 2. jp2 (avdd_sel) : avdd of the AK5701 open : avdd is supplied from the regulator (?avdd? jack should be open). < default > short : avdd is supplied from ?avdd ? jack. 3. jp3 (dvdd_sel) : dvdd of the AK5701 avdd : dvdd is supplied from ?avdd?. < default > dvdd : dvdd is supplied from ?dvdd ? jack. 4. jp4 (csp) : csp signal select (hi or low) h : csp= ?hi? l : csp= ?low?< default > 5. jp5, jp6 (mpwr) : connect to mpwr open : no connect< default > short : connect 6. jp7 (lvc_sel) : supply line selection of logic block of lvc. dvdd : logic block of lvc is supplied from ?dvdd?. < default > vd : logic block of lvc is supplied from ?vd ? jack. 7. jp20 (sdto) : select #4 pin of the port4 (dsp) open : input data for exsdti short : output data for sdto of the port4 8. jp8 (cclk) : cclk select open : no connect short : cclk connect
asahi kasei [akd5701-a] 2006 / 06 - 12 - ? the function of the toggle sw [sw1] (dit): power control of ak4114. keep ?h? during normal operation. keep ?l? when ak4114 is not used. [sw3] (pdn): power control of AK5701. keep ?h? during normal operation. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when some error has occurred to ak4114. ? serial control the AK5701 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 (ctrl) with pc by 10-wire flat cable packed with the akd5701-a 10pin header csn 10 wire flat cable cclk cdti 10pin connector pc connect a kd5701-a figure 2. connect of 10 wire flat cable
asahi kasei [akd5701-a] 2006 / 06 - 13 - ? analog input / output circuits (1) input circuits a) lin, rin, mic input circuit lin1 j1 mr-552ls lin 3 2 lin2 jp9 lin lin2 lin1 rin1 j2 mr-552ls 2 rin 3 rin2 jp10 rin rin2 rin1 1 1 4 6 3 j5 mic r38 (open) r39 (open) figure 3. lin, rin, mic input circuit (a-1) lin1, rin1 input jp9 lin lin2 lin1 rin2 rin1 rin jp10 (a-2) lin2, rin2 input jp9 lin lin2 lin1 rin2 rin1 rin jp10 ? akm assumes no responsibility for the trouble when using the above circuit examples.
asahi kasei [akd5701-a] 2006 / 06 - 14 - 2. control software manual ? set-up of evaluation board and control software 1. set up the akd5701-a according to previous term. 2. connect ibm-at compatible pc with akd5701-a by 10- line type flat cable (packed with akd5701-a). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?AK5701 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd5701-a.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. 3. click ?write default? button ? explanation of each buttons 1. [port reset] : set up the usb interf ace board (akdusbif-a) when using the board. 2. [write default] : initialize the register of AK5701-a. 3. [all write] : write all registers that is currently displayed. 4. [function1] : dialog to write data by keyboard operation. 5. [function2] : dialog to write data by keyboard operation. 6. [function3] : the sequence of regi ster setting can be set and executed. 7. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the re gister setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save] : save the current register setting. 10. [open] : write the saved values to all register. 11. [write] : dialog to write data by mouse operation. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
asahi kasei [akd5701-a] 2006 / 06 - 15 - ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to AK5701, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to AK5701, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate ivol there are dialogs corresponding to register of 18h and 19h. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is wr itten to AK5701 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not re turn to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to AK5701, click [ok] button. if not, click [cancel] button.
asahi kasei [akd5701-a] 2006 / 06 - 16 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the AK5701. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.ak r) and click [open] button.
asahi kasei [akd5701-a] 2006 / 06 - 17 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. the following is displayed. (2) set the control sequence. set the address, data and interval time. set ?-1? to th e address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [o pen] button on the function3 window. the extension of file name is ?aks?. figure 1. window of [f3]
asahi kasei [akd5701-a] 2006 / 06 - 18 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be liste d up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 2 opens. figure 2. [f4] window
asahi kasei [akd5701-a] 2006 / 06 - 19 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the se quence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 3. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 3. [f4] window(2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [func tion4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence f ile (*.aks) should be loaded again in order to reflect the change.
asahi kasei [akd5701-a] 2006 / 06 - 20 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 4 opens. figure 4. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 5. (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
asahi kasei [akd5701-a] 2006 / 06 - 21 - figure 5. [f5] windows(2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displaye d on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register setting file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is change d by [save] button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
asahi kasei [akd5701-a] 2006 / 06 - 22 - measurement results 1.AK5701 mode: ext mode (slave) [measurement condition] ? measurement unit: ap2 (audio precision, system two, cascade) ? mcki: 256fs ? bclk: 64fs ? bit: 16bit ? sampling frequency: 44.1khz ? measurement frequency: 20 20khz ? power supply: avdd=dvdd=vd=3.0v ? temperature: room ? input frequency: 1khz [measurement results] 1.adc characteristics (mic gain = 0db, ivol=0db, alc = off, lin/rin ? adc) result mgain=0db mgain=+15db lin rin lin rin s/(n+d) (-0.5dbfs) 79.0db 79.0db 78.3db 78.4db d-range (-60dbfs) 89.8db 89.8db 87.7db 87.7db s/n 89.9db 89.8db 87.7db 87.7db 2. AK5701 mode: pll master mode [measurement condition] ? measurement unit: ap2 (audio precision, system two, cascade) ? mcki: 12mhz ? bclk: 64fs ? bit: 16bit ? sampling frequency: 44.0995khz ? measurement frequency: 20 20khz ? power supply: avdd=dvdd=vd=3.0v ? temperature: room ? input frequency: 1khz [measurement results] adc characteristics result mgain=0db mgain=+15db lin rin lin rin s/(n+d) (-0.5dbfs) 78.7db 78.3db 77.9db 77.5db d-range (-60dbfs) 89.3db 89.3db 87.4db 87.3db s/n 89.3db 89.3db 87.4db 87.3db
asahi kasei [akd5701-a] 2006 / 06 - 23 - 3. plot data < ( b j o e # > akm AK5701 thd+n vs input level (fin=1khz, gain=0db) -100 -60 -96 -92 -88 -84 -80 -76 -72 -68 -64 d b f s -120 -10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbr figure 1. thd+n vs. input level akm AK5701 thd+n vs frequency (fin=1khz, gain=0db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -60 -96 -92 -88 -84 -80 -76 -72 -68 -64 d b f s figure 2. thd+n vs. input frequency
asahi kasei [akd5701-a] 2006 / 06 - 24 - akm AK5701 linearity (fin=1khz, gain=0db) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -120 +0 -108 -96 -84 -72 -60 -48 -36 -24 -12 d b f s 5 5 5 5 5 figure 3. linearity akm AK5701 freqency responce (fin=1khz, gain=0db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 d b f s figure 4. frequency response
asahi kasei [akd5701-a] 2006 / 06 - 25 - akm AK5701 crosstalk (fin=1khz, gain=0db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -60 -132 -124 -116 -108 -100 -92 -84 -76 -68 d b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 figure 5. crosstalk akm AK5701 fft s/(n+d) -0.5dbfs (fin=1khz, gain=0db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 -0 -144 -128 -112 -96 -80 -64 -48 -32 -16 d b f s figure 6. fft plot
asahi kasei [akd5701-a] 2006 / 06 - 26 - akm AK5701 fft dr (fin=1khz, gain=0db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 -0 -144 -128 -112 -96 -80 -64 -48 -32 -16 d b f s figure 7. fft plot akm AK5701 fft s/n mgain=0db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 8. fft plot
asahi kasei [akd5701-a] 2006 / 06 - 27 - < ( b j o e # > akm AK5701 thd+n vs input level mgain=+15db -120 -10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbr -100 -60 -96 -92 -88 -84 -80 -76 -72 -68 -64 d b f s figure 9. thd+n vs. input level akm AK5701 thd+n vs freqency (fin=1khz, gain=+15db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -60 -96 -92 -88 -84 -80 -76 -72 -68 -64 d b f s figure 10. thd+n vs. input frequency
asahi kasei [akd5701-a] 2006 / 06 - 28 - akm AK5701 lineearity (fin=1khz, gain=+15db) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -120 +0 -108 -96 -84 -72 -60 -48 -36 -24 -12 d b f s 5 5 5 figure 11. linearity akm AK5701 freqency responce (fin=1khz, gain=+15db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 d b f s figure 12.freqency response
asahi kasei [akd5701-a] 2006 / 06 - 29 - akm AK5701 crosstalk (fin=1khz, gain=+15db) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -60 -132 -124 -116 -108 -100 -92 -84 -76 -68 d b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 figure 13.crosstalk akm AK5701 fft s/(n+d) -0.5dbfs mgain=+15db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 14. fft plot
asahi kasei [akd5701-a] 2006 / 06 - 30 - akm AK5701 fft dr mgain=+15db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 15. fft plot akm AK5701 fft s/n mgain=+15db 20 20k 50 100 200 500 1k 2k 5k 10k hz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 16. fft plot
asahi kasei [akd5701-a] 2006 / 06 - 31 - revision history date manual revision board revision reason contents 05/04/25 km076903 0 first edition 06/06/26 km076904 1 circuit change c28,29 open -> 10pf important notice ? these products and their specific ations are subject to change with out notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concer ning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them , may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for us e as critical components in any safety, life support, or other hazard related device or syst em, and akm assumes no responsibility relating to any such use, except with the express written cons ent of the representative director of akm. as used here: (a) a hazard related device or system is one design ed or intended for life support or maintenance of safety or for applications in medicine, aerospace , nuclear energy, or other fields, in which its failure to function or perform may reasonably be expe cted to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to f unction or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore me et very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a reg_in avdd1 dvdd1 vd1 reg_in avdd1 dvdd1 vd1 cclk avdd cdti csn avdd dvdd vd dvdd mcko sdto 5701_mcki avdd 5701_exsdti 5701_exlrck 5701_exbclk pdn lin1 rin1 lin2 rin2 lvc bclk lrck title size document number rev date: sheet of AK5701 1 akd5701-a a3 15 monday, june 26, 2006 title size document number rev date: sheet of AK5701 1 akd5701-a a3 15 monday, june 26, 2006 title size document number rev date: sheet of AK5701 1 akd5701-a a3 15 monday, june 26, 2006 reg dvdd avdd h l dvdd vd r1 5.1 r1 5.1 24 23 22 21 20 19 cn4 24pin_4 cn4 24pin_4 c2 0.1u c2 0.1u in out gnd t1 ta48033f t1 ta48033f 1 2 l3 (short) l3 (short) jp7 lvc_sel jp7 lvc_sel r13 51 r13 51 r7 51 r7 51 jp2 avdd_sel jp2 avdd_sel jp6 mpwr jp6 mpwr vcoc 24 vcom 1 avss 2 avdd 3 dvdd 4 dvss 5 bclk 6 mcki 14 cdti 15 cclk 16 csn 17 pdn 18 exbclk 13 lin1 23 rin1 22 lin2 21 rin2 20 mpwr 19 lrck 7 sdto 8 csp 9 mcko 10 exsdti 11 exlrck 12 AK5701 u1 AK5701 u1 1 2 + c4 47u + c4 47u jp4 csp jp4 csp r3 51 r3 51 r10 2.2k r10 2.2k 1 2 3 4 5 6 cn1 24pin_1 cn1 24pin_1 r14 51 r14 51 r8 51 r8 51 1 reg1 t45_r reg1 t45_r r18 (open) r18 (open) r16 51 r16 51 r2 51 r2 51 jp1 gnd jp1 gnd r5 51 r5 51 1 2 + c17 1u + c17 1u 1 2 + c7 2.2u + c7 2.2u r6 51 r6 51 c10 0.1u c10 0.1u 1 2 + c14 1u + c14 1u r9 51 r9 51 r11 2.2k r11 2.2k 1 2 + c5 10u + c5 10u 1 2 + c18 47u + c18 47u c8 0.1u c8 0.1u 1 agnd1 t45_bk agnd1 t45_bk 1 2 + c15 1u + c15 1u r12 51 r12 51 jp3 dvdd_sel jp3 dvdd_sel 1 2 + c12 47u + c12 47u r17 (open) r17 (open) 1 2 l2 (short) l2 (short) 1 dvdd1 t45_o dvdd1 t45_o r15 51 r15 51 jp5 mpwr jp5 mpwr 1 dgnd1 t45_bk dgnd1 t45_bk 1 2 l1 (short) l1 (short) c13 4.7n c13 4.7n 13 14 15 16 17 18 cn3 24pin_3 cn3 24pin_3 r4 10k r4 10k 7 8 9 10 11 12 cn2 24pin_2 cn2 24pin_2 c11 (open) c11 (open) 1 vd1 t45_o vd1 t45_o 1 avdd1 t45_o avdd1 t45_o jp8 cclk jp8 cclk c1 0.1u c1 0.1u c9 0.1u c9 0.1u r40 51 r40 51 1 2 + c16 1u + c16 1u 1 2 + c3 47u + c3 47u 1 2 + c6 10u + c6 10u
a a b b c c d d e e e e d d c c b b a a lin1 lin2 rin1 rin2 title size document number rev date: sheet of input 1 akd5701-a a3 25 monday, june 26, 2006 title size document number rev date: sheet of input 1 akd5701-a a3 25 monday, june 26, 2006 title size document number rev date: sheet of input 1 akd5701-a a3 25 monday, june 26, 2006 lin lin1 lin2 rin rin1 rin2 r38 (open) r38 (open) 2 3 1 j1 mr-552ls j1 mr-552ls r39 (open) r39 (open) 2 3 1 j2 mr-552ls j2 mr-552ls jp9 lin jp9 lin jp10 rin jp10 rin 6 4 3 j5 mic j5 mic
a a b b c c d d e e e e d d c c b b a a vd vd ext_bclk mcko mcki ext_lrck vd extclk/lrck extclk/bclk ext_mclk lvc title size document number rev date: sheet of clock 1 akd5701-a a3 35 monday, june 26, 2006 title size document number rev date: sheet of clock 1 akd5701-a a3 35 monday, june 26, 2006 title size document number rev date: sheet of clock 1 akd5701-a a3 35 monday, june 26, 2006 1024fs 64fs 512fs 256fs 32fs 16fs 1fs for 74ac74,74vhc4040,74hc14 mcko ext/bclk avss ext/lrck 2fs for 74lvc07ans 2 3 1 j4 mr-552ls j4 mr-552ls 2 3 1 j3 mr-552ls j3 mr-552ls jp14 ext1 jp14 ext1 c21 0.1u c21 0.1u d 12 clk 11 q 9 q 8 pr 10 cl 13 u3b 74ac74 u3b 74ac74 1 2 + c23 47u + c23 47u c19 0.1u c19 0.1u jp13 lrck_sel jp13 lrck_sel c22 0.1u c22 0.1u jp12 blck_sel jp12 blck_sel r20 51 r20 51 d 2 clk 3 q 5 q 6 pr 4 cl 1 u3a 74ac74 u3a 74ac74 jp11 mkfs jp11 mkfs r21 51 r21 51 r19 short r19 short c20 0.1u c20 0.1u clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 u2 74vhc4040 u2 74vhc4040 jp15 ext2 jp15 ext2
a a b b c c d d e e e e d d c c b b a a daux vd vd vd ocks0 ocks1 vd vd vd vd vd ocks1 ocks0 4114_mcko extclk/bclk 5701_mcko 4114_bick 4114_lrck title size document number rev date: sheet of dit 1 akd5701-a a3 45 monday, june 26, 2006 title size document number rev date: sheet of dit 1 akd5701-a a3 45 monday, june 26, 2006 title size document number rev date: sheet of dit 1 akd5701-a a3 45 monday, june 26, 2006 h l dif0 ocks1 dif1 ocks0 1 2 + c24 10u + c24 10u c27 0.47u c27 0.47u ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 u5 ak4114 u5 ak4114 c26 0.1u c26 0.1u 1 2 + c32 10u + c32 10u k a d1 hsu119 d1 hsu119 c30 0.1u c30 0.1u c34 0.1u c34 0.1u c29 5p c29 5p 1 2 + c33 10u + c33 10u c31 0.1u c31 0.1u c28 5p c28 5p c25 0.1u c25 0.1u 1 2 3 4 8 7 6 5 sw2 mode2 sw2 mode2 r24 1k r24 1k 1 2 u4a 74hc14 u4a 74hc14 1 2 x1 11.2896mhz x1 11.2896mhz k a led1 erf led1 erf r23 18k r23 18k r22 10k r22 10k jp16 xti jp16 xti 3 4 u4b 74hc14 u4b 74hc14 2 1 3 sw1 dit sw1 dit gnd 1 vcc 2 in 3 port1 totx141 port1 totx141 5 6 u4c 74hc14 u4c 74hc14 1 2 3 4 5 rp1 47k rp1 47k
a a b b c c d d e e e e d d c c b b a a 5701_exsdti 5701_exlrck 5701_exbclk ext_bclk 4114_lrck ext_lrck 4114_bick vd lvc vd vd 5701_mcki csn cclk cdti pdn vd daux 4114_mcko exsdti bclk lrck sdto mcko 5701_mcko exsdti extclk/lrck vd mcki extclk/bclk ext_mclk extclk/bclk title size document number rev date: sheet of logic 1 akd5701-a a3 55 monday, june 26, 2006 title size document number rev date: sheet of logic 1 akd5701-a a3 55 monday, june 26, 2006 title size document number rev date: sheet of logic 1 akd5701-a a3 55 monday, june 26, 2006 exlrck ext mcki vd exsdti exbclk cclk cdti csn lh ext exbclk-dit mcki bclk lrck vd sdto bclk-dit extlrclk exlrck-dit lrck-dit sdto extbclk r26 330 r26 330 jp19 mcki_sel jp19 mcki_sel c37 0.1u c37 0.1u 9 8 u7d 74lvc07ans u7d 74lvc07ans 1 2 3 4 5 6 7 8 9 10 port3 ctrl port3 ctrl c35 0.1u c35 0.1u r36 10k r36 10k r34 470 r34 470 1 2 3 4 5 6 7 8 9 10 port4 dsp2 port4 dsp2 9 8 u4d 74hc14 u4d 74hc14 2 1 3 sw3 pdn sw3 pdn r28 330 r28 330 r30 10k r30 10k 11 10 u4e 74hc14 u4e 74hc14 r35 470 r35 470 13 12 u4f 74hc14 u4f 74hc14 r31 10k r31 10k a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u6 74lvc541 u6 74lvc541 13 12 u7f 74lvc07ans u7f 74lvc07ans jp20 sdto jp20 sdto r37 10k r37 10k r33 10k r33 10k 1 2 u7a 74lvc07ans u7a 74lvc07ans jp18 lrck_sel jp18 lrck_sel k a d2 hsu119 d2 hsu119 r32 470 r32 470 1 2 3 4 5 6 7 8 9 10 port2 dsp1 port2 dsp1 r27 330 r27 330 1 2 + c36 47u + c36 47u r25 330 r25 330 jp17 bclk_sel jp17 bclk_sel 3 4 u7b 74lvc07ans u7b 74lvc07ans r29 10k r29 10k 11 10 u7e 74lvc07ans u7e 74lvc07ans 5 6 u7c 74lvc07ans u7c 74lvc07ans
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